Those who are interested can send their profiles to Mr. Srikanth Vadanapathi.
Regards
> Begin forwarded message:
> From: Srikanth Vadanaparthi <
Srikanth.Vadanaparthi@synopsys.com>Date: 2
> February 2010 6:26:52 PM GMT+05:30
Subject: FW: Action Requested: Soliciting Referral
> Resume
> Hello all
> ,
> If any of
> your friends are interested for this positions. Kindly send
> the resume asap.
> -----------------------------------------------------------------------------------------------------------------------------------------------------Dear
> Colleagues,
> As you
> may be aware, we have grown and built a strong team in the
> last several years through Employee
> Referral……
> The
> purpose of this mail is to solicit help from you for hiring
> TWO key positions in our team for a new initiative. This new
> initiative is: develop "DW minPower
> Libraries", which is part of the
> DW Libraries product line. The details for the TWO
> positions, R&D
> Engineer/Sr R&D Engineer in SG are as
> follows:
> Job
> Responsibilities:Responsible for design, verification and
> documentation of configurable block-level and medium
> complexity core-level designs to be part of Synopsys Design
> Ware Building Block IP Library. Medium complexity core-level
> design will be concentrated around DSP blocks used in WL
> communication systems, Multimedia systems and High speed
> wired line communication systems. Work will primarily
> involve Verilog RTL coding for synthesis - although some
> behavioral coding in both Verilog and VHDL may be required
> for block- level component projects. Verification work will
> involve traditional test-bench simulation, formal methods
> and some hardware verification through FPGA
> implementation.
> Job
> Requirements:Experience in RTL level ASIC design. The
> candidate should be highly proficient in Verilog RTL design
> for synthesis and have good working knowledge of
> Verilog/VHDL coding. A candidate who is technically detail
> oriented and a quick learner is best suited for this
> position. The candidate should be familiar with ASIC design
> flow and fundamentals of design, verification. Experience
> in implementation of DSP blocks such as FFT, DCT, Equalizer,
> etc. is a plus. Experience with configurable design
> techniques would be a strong plus. Knowledge and experience
> with Synopsys tools (especially Design Compiler and VCS)
> preferred.Exp :
> 5-9 yrs
> Please
> Note: The R&D Engineer will
> primarily focus on the RTL implementation and hence it is essential to have strong
> RTL design, implementation and basic verification skills; We
> would like the Sr R&D Engineer to contribute to core
> specifications and system level understanding. Hence,
> domain expertise i.e. WL communication
> systems/ Multimedia systems/ High Speed Wired Line
> communication is very
> important. Thanks & regards
> ,Srikanth
> V
>
>
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>
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>
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