| Below are some openings @synopsys. if any of you or your friends are interested kindly send the resume to 1.CAE -Hyderbad Provides post-sales technical expertise during the installation, implementation, and maintenance of company products. May be involved in implementing detailed customer installation requirements. Ensures that client's needs have been met and that the product/solution is fully functioning according to specification. May provide pre-sales support to company sales staff and customer personnel.
Typically requires a minimum of 2 years of related experience. Developing professional expertise, applies company policies and procedures to resolve a variety of issues. Has working knowledge of work area and general proficiency with tools, systems, and procedures required to accomplish the job. Exercises judgment within defined procedures and practices to determine appropriate action. Receives general instructions on routine work, detailed instructions on new assignments. Implementations and solutions are reviewed for accuracy and overall adequacy. Builds productive internal/external working relationships. Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters. Has a basic overall understanding of the design process. Strong communication skills are required. Requirements: 2 - 10 years experience in Microprocessor / DSP Hardware development and support. Usage of RTL coding (Verilog, System Verilog, VHDL), logic simulation and synthesis , timing analysis, and verification methodologies (Synopsys/Cadence). Knowledge of silicon level implications on area, low power, speed performance criteria. Strong problem solving ability and debug through verification capability. Solid outward bound communication skills and follow-up initiative. Domain knowledge of ISS (instruction Set Simulator) and FPGA emulation / advanced RTL -> C acceleration a strong plus. Knowledge using compilers, linkers, assemblers and debuggers and run subset test programs on CPU core in C/C++ and assembly code an added plus. Ability to drive next-generation architectures in conjunction with world-wide customer base, internal Research and Development, and business functions. 2. R&D bangalore Description: Responsible for development (implementation & verification) of Verification IP. Expected to be proficient in programming and software development. Expected to follow good coding practices. Given the feature requirement, will work to define functional specification, design specification, implementation & verification of the feature. Expected to be good at problem solving and debugging. Would work in a multi-site environment, with teams across time zones. May need some interaction with applications engineering teams, and customers, on need basis. Expected to have good communication skills. Requirements: Must have BS in CS/EE with at least 4+ years of relevant experience or MS with at least 2+ years of relevant experience in one or more of the following areas: · Essential knowledge of HVL/HDVL like OpenVera, e, SystemVerilog · Familiarity with atleast one indutry standard verification methodology like RVM, VMM, OVM, etc. · Strong in Object Oriented Programming concepts · Familiarity with development of verification strategy, test plan, coverage, verification environment · Familiarity with any one industry popular simulator tools like VCS, MTI, NC · Knowledge of HDLs like Verilog/VHDL will be an added advantage Knowledge of MIPI (CSI, DSI and DigRF ) domain will be of critical advantage 3.CAE -bangalore Requisition Description As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. You will be interfacing with our Design Engineering team to report on any issues related to the IP's design, reliability and maintenance or defects. You will have the capability to design and implement solutions to complex application problems independently with little guidance. You will be authoring application-notes and/or white-papers that promote the IP's ease of use, or address specific challenges in the IP's usage. You may be called upon to author technical papers and present them in peer-reviewed technical publications or conferences. You will have regular contact with external customers and internal contacts across cross-functional teams. Requisition Requirements Qualified applicants will have a BSEE, MSEE, + 5 years relevant experience in ASIC design. Overall understanding of the ASIC design process is required. Strong communication skills and ability to interact with customers as well as peers is required. Must be proficient with C/C++/tcl/Perl, Unix, Verilog HDL. Knowledge of competitive EDA tool products and product knowledge in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired. Domain knowledge of the DDRn Protocol with relevant experience is required. Debug and troubleshooting skills are highly desirable. Occasional travel will be required. 4. R&D - bangalore The candidate will be responsible for design, implementation, and maintenance working on the Synopsys IP reuse tools whose focus is to enable the deployment of highly configurable RTL components and the automated assembly of these components into large subsystems. The candidate is expected to design, implement, and test in a large and complex software development environment split between C++ and TCL. The candidate should have a strong desire to produce high quality code and be motivated to develop a strong understanding of the product domain to ensure that point solutions fit properly into the larger context of how the tools are used. Requirements: - BS in CS/EE with 5+ years of relevant experience or MS with 2+ years of relevant experience. - Strong C++ and TCL programming skills. - Solid problem solving and debugging skills are required. - Must be familiar with software development processes and associated tools. - Familiarity with hardware description languages is desired. - Exposure to IP design or SoC assembly tools and processes would be ideal. 5.R&D Bangalore Description: Responsible for playing technical architect role and development (implementation & verification) of Verification IP. Expected to be proficient in programming and software development. Expected to follow good coding practices. Given the feature requirement, will work to define functional specification, design specification, implementation & verification of the feature. Expected to be good at problem solving and debugging. Would work in a multi-site environment, with teams across time zones. Able to drive technical and review closure of implementations by engineering team and able to interact with applications engineering teams, and customers, for seeking/proposing technical solutions for verification problems. Expected to have good communication skills. Requirements: Must have BS in CS/EE with at least 8+ years of relevant experience or MS with at least 6+ years of relevant experience in one or more of the following areas: · Essential knowledge of HVL/HDVL like OpenVera, e, SystemVerilog · Familiarity with atleast one indutry standard verification methodology like RVM, VMM, OVM, etc. and development experience of VIP will be an added advantage. · Strong in Object Oriented Programming concepts · Familiarity with development of verification strategy, test plan, coverage, verification environment · Familiarity with any one industry popular simulator tools like VCS, MTI, NC · Knowledge of HDLs like Verilog/VHDL will be an added advantage · Knowledge of MIPI (CSI, DSI, DigRF) domain will be of critical advantage |
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